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    • 专利摘要:
    The invention relates to a display device comprising a first integrated circuit (200) comprising: a set of light-emitting diodes (103), each diode comprising a vertical stack of a first semiconductor layer (105) of a first conductivity type and a second semiconductor layer (109) of the second conductivity type; and on one side of the first circuit opposite the first semiconductor layer (105), a connection structure (201) comprising a dielectric layer (203) in which a plurality of identical or similar connection pads (205) are disposed , regularly distributed over the entire surface of the first circuit, each diode (103) having a first electrode (111) in contact with at least one pad (205) of the connection structure (201), and a second electrode (113) in contact with a plurality of pads (205) of the connection structure (201) at the periphery of the plurality of diodes.
    公开号:FR3079350A1
    申请号:FR1852465
    申请日:2018-03-22
    公开日:2019-09-27
    发明作者:Francois Templier；Severine Cheramy；Frank Fournel
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    EMISSIBLE LED DISPLAY DEVICE AND METHOD FOR MANUFACTURING SUCH A DEVICE
    Field
    The present application relates to the field of optoelectronic devices. It relates more particularly to an emissive display device with light-emitting diodes (LED), also called micro-LED screen, and a method of manufacturing such a device.
    Presentation of the prior art
    An emissive display device has already been proposed comprising a set of several LEDs, for example with gallium nitride, and a control circuit making it possible to individually control the LEDs for displaying images.
    We are particularly interested here in the case where the control circuit is integrated in and on a semiconductor substrate, for example a silicon substrate, for example in CMOS technology.
    To make such a device, provision may be made to manufacture the control circuit and the LED assembly separately, then to connect them to each other to form the display device. On the side of one of its faces, the control circuit comprises a plurality of metal pads, each pad being intended to be connected to an electrode of an LED of the assembly
    B16845 - DD18591 of LEDs, to be able to control the LEDs individually. The set of LEDs is for example produced in a monolithic fashion on a support substrate, then added to the control circuit so that each LED has an electrode (anode or cathode) connected to one of the metal pads of the control circuit .
    One difficulty lies in the need to precisely align the control circuit and the set of LEDs during the step of assembling these two elements, so that each LED is positioned correctly on the metal stud which corresponds to it in the control circuit. This alignment is particularly difficult to achieve when the pixel pitch decreases, and constitutes a brake on the increase in the resolution and / or the integration density of the pixels.
    summary
    Thus, one embodiment provides a display device comprising a first integrated circuit comprising:
    a set of several light-emitting diodes, each diode comprising a vertical stack of a first semiconductor layer of a first conductivity type and of a second semiconductor layer of the second type of conductivity, and the diodes being separated from each other by trenches r
    for each diode, a first electrode disposed on and in contact with the face of the second layer opposite to the first layer;
    a second electrode common to said plurality of diodes, the second electrode extending in the trenches and at the periphery of the plurality of diodes and being in contact, in each diode, with the first semiconductor layer; and on the side of a face of the first circuit opposite the first semiconductor layer, a connection structure comprising a dielectric layer in which are arranged a plurality of identical or similar connection pads, regularly distributed over the entire surface of the first circuit,
    B16845 - DD18591 each diode having its first electrode in contact with at least one stud of the connection structure, and the second electrode being in contact with several studs of the connection structure at the periphery of the plurality of diodes.
    According to one embodiment, the device further comprises a second integrated circuit formed in and on a semiconductor substrate, the second circuit comprising, for each diode of the first circuit, a metal pad intended to be connected to the first electrode of the diode, and a metal electrode intended to be connected to the second electrode of the first circuit.
    According to one embodiment, the first and second circuits are fixed to each other by direct hybrid bonding so that each first electrode of the first circuit is electrically connected to a metal pad of the second circuit, and that the second electrode of the first circuit is electrically connected to the electrode of the second circuit.
    According to one embodiment, the second circuit comprises a connection structure comprising a dielectric layer in which are arranged a plurality of identical or similar connection pads, regularly distributed over the entire surface of the second circuit, each metal pad of the second circuit being contact with at least one connection pad of the connection structure of the second circuit, and the electrode of the second circuit being in contact with several connection pads of the connection structure of the second circuit in a peripheral region of the electrode of the second circuit.
    According to one embodiment, the second circuit comprises, for each metal pad of the second circuit, an elementary control cell comprising one or more transistors, making it possible to control the current flowing in the corresponding diode of the first circuit and / or a voltage applied to the terminals of the corresponding diode of the first circuit.
    B16845 - DD18591
    According to one embodiment, the second circuit is produced using CMOS technology.
    According to one embodiment, the diodes of the first circuit are gallium nitride diodes.
    According to one embodiment, in the first circuit, each light-emitting diode further comprises an emissive layer between the first and second semiconductor layers of the diode.
    Another embodiment provides a method of manufacturing a display device as defined above, in which the formation of the first circuit comprises the following successive steps:
    a) successively depositing, on one face of a support substrate, a vertical stack comprising, in order from said face of the substrate, the first and second semiconductor layers and a metal layer;
    b) forming, from the face of the stack opposite the support substrate, trenches crossing said stack over its entire height and delimiting the different diodes of the first circuit; and
    c) forming, in said trenches, a metallization in contact, at each diode, with the first semiconductor layer of the stack.
    According to one embodiment, step b) comprises a first step of partial formation of the trenches up to an intermediate level of the first semiconductor layer, followed by a step of depositing an insulating layer on the sides of the trenches, followed by a step of extending the trenches to the underside of the first semiconductor layer.
    According to one embodiment, the metallization formed in step c) extends over the entire height of the trench.
    According to one embodiment, the metallization formed in step c) extends over only part of the height of the trenches, up to an intermediate level of the first layer
    B16845 - DD18591 semiconductor, the upper part of the trenches being filled with an insulating material.
    Brief description of the drawings
    These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments made without implied limitation in relation to the attached figures, among which:
    Figures IA and IB are sectional views schematically and partially illustrating successive steps of an example of a method of manufacturing an emissive LED display device;
    FIGS. 2A and 2B are sectional views schematically and partially illustrating successive steps of an example of a method for manufacturing an emissive LED display device according to one embodiment;
    Figures 3A, 3B, 3C, 3D, 3E, 3F and 3G are sectional views illustrating in more detail successive steps of an example of a method of manufacturing an emissive LED display device according to a mode of achievement; and FIGS. 4A, 4B, 4C, 4D, 4E and 4F are sectional views illustrating successive steps of another example of a method of manufacturing an emissive LED display device according to one embodiment.
    detailed description
    The same elements have been designated by the same references in the different figures and, moreover, the various figures are not drawn to scale. For the sake of clarity, only the elements useful for understanding the described embodiments have been shown and are detailed. In particular, the production of an integrated LED control circuit has not been detailed, the embodiments described being compatible with the usual structures and methods of manufacturing such control circuits. In addition, the composition and arrangement of the different layers of an active stack of LEDs have not been detailed, the embodiments described being
    B16845 - DD18591 compatible with the usual active LED stacks. In the following description, when referring to qualifiers of absolute position, such as the terms forward, backward, up, down, left, right, etc., or relative, such as the terms above, below, upper , lower, etc., or to orientation qualifiers, such as the terms horizontal, vertical, etc., reference is made to the orientation of the figures, it being understood that, in practice, the devices and assemblies described can be oriented differently. Unless specified otherwise, the expressions approximately, substantially, and of the order of mean to 10%, preferably to 5%.
    Figures IA and IB are sectional views schematically and partially illustrating successive steps of an example of a method of manufacturing an emissive LED display device.
    FIG. 1A illustrates an initial step during which a first integrated circuit 100 comprising a plurality of LEDs is manufactured, separately, and a second integrated circuit 150, corresponding to the LED control circuit.
    The circuit 100 comprises a support substrate 101, for example made of sapphire, silicon, gallium nitride (GaN), or any other material on which an active stack of LEDs can be deposited. The circuit 100 further comprises a plurality of LEDs 103, for example identical or similar, arranged on the upper face of the support substrate 101. Seen from above, the LEDs 103 are for example arranged in an array in rows and columns, by example regularly distributed on the upper face of the substrate 101. Each LED 103 comprises a vertical stack comprising, in order from the upper face of the substrate 101, a first semiconductor layer 105 doped with a first type of conductivity, for example of type N, an emissive layer 107, and a second semiconductor layer 109 doped with the second type of conductivity, for example of type P. The layers 105 and 109 are for example of gallium nitride. The
    B16845 - DD18591 emissive layer 107 is for example constituted by a stack of one or more emissive layers each forming a quantum well, for example based on GaN, InN, InGaN, AlGaN, AIN, AlInGaN, GaP, AlGaP, AlInGaP, or of a combination of one or more of these materials. As a variant, the emissive layer 107 can be a layer of intrinsic gallium nitride, that is to say unintentionally doped. More generally, a person skilled in the art will know how to choose the material or materials of the emissive layer 107 as a function of the desired emission wavelength, for example for emission in the visible range, in the ultraviolet range, or in the infrared domain.
    In this example, the lower face of the emissive layer 107 is in contact with the upper face of the layer 105, and the upper face of the emissive layer 107 is in contact with the lower face of the layer 109. In practice, depending on the nature of the substrate 101, a stack of one or more buffer layers (not shown) can interface between the support substrate 101 and the semiconductor layer 105.
    The elementary LEDs 103 of the circuit 100 are separated from each other by vertical trenches extending, in this example, over the entire thickness of the stack of layers 105, 107 and 109 and opening onto the upper face of the substrate support 101 or, where appropriate, of the buffer layer (not shown) separating the support substrate 101 from the semiconductor layer 105. More particularly, in this example, the LED separation trenches form, seen from above, a grid like that each mesh of the grid comprises a single LED 103, and such that each LED 103 is arranged in a mesh of the grid.
    The circuit 100 includes, for each LED 103, a metal electrode 111 disposed on and in contact with the upper face of the semiconductor layer 109 of the LED. In this example, the electrode 111 extends over the entire upper surface of the semiconductor layer 109 of the LED.
    B16845 - DD18591
    The circuit 100 further comprises a metal electrode 113 common to the set of LEDs 103. The electrode 113 extends in the trenches separating the LEDs 103 and at the periphery of the set of LEDs 103. Seen from above, the electrode 113 forms a continuous grid such that each mesh of the grid contains a single LED 103, and such that each LED 103 is arranged in a mesh of the grid. In each LED 103, the lower semiconductor layer 105 of the LED is in contact with the common electrode 113. More particularly, in the example shown, in each LED 103, the electrode 113 is in contact with a lower part of the sides of the semiconductor layer 105 of the LED, over the entire periphery of the LED. In this example, each LED 103 further comprises, in an upper part of the LED, a peripheral insulation wall 115, made of a dielectric material, in contact, over the entire periphery of the LED, with the sides of the electrode upper 111, the semiconductor layer 109 and the emissive layer 107 of the LED, as well as with an upper part of the sides of the semiconductor layer 105 of the LED. The peripheral insulation wall 115 in particular makes it possible to electrically isolate the electrode 113 from the electrode 111 and layers 109 and 107 of the LED.
    In this example, the upper face of the electrode 113, the upper faces of the electrodes 109, and the upper faces of the insulation walls 115 are substantially at the same level (that is to say substantially coplanar) and define a substantially continuous surface. plane, forming the connection face of the circuit 100. Thus, the connection face of the circuit 100 comprises alternating metal regions (the electrodes 111 and 113) and dielectric regions (the insulation walls 115).
    The control circuit 150 is formed in and on a semiconductor substrate 151, for example a silicon substrate. In this example, the control circuit 150 comprises, on the side of its upper face, for each of the LEDs of the circuit 100, a metallic connection pad 161 intended to be connected to the electrode 111 of the LED, so as to be able to control a circulating current
    B16845 - DD18591 in the LED and / or apply a voltage across the LED. The control circuit 150 comprises for example, for each LED, connected to the metal pad 161 dedicated to the LED, an elementary control cell (not detailed) comprising one or more transistors, making it possible to control the current flowing in the LED and / or a voltage applied to the terminals of the LED. The control circuit 150 is for example made of CMOS technology.
    In the example shown, the control circuit 150 further comprises, on the side of its upper face, a metal electrode 163 intended to be connected to the common electrode 113 of the LED circuit 100. Each elementary control cell of the circuit 150 is for example connected to the electrode 163.
    In the example shown, the pads 161 and the electrode 163 of the integrated circuit 150 have, in top view, substantially the same dimensions and the same arrangement as the electrodes 111 and 113 of the LED circuit 100. In other words, in this example, seen from above, the electrode 163 forms a continuous grid such that each mesh of the grid contains a single stud 161, and such that each stud 161 is arranged in a mesh of the grid.
    The pads 161 are separated laterally from the electrode 163 by a ring 165 of dielectric material, for example silicon oxide. In this example, the rings 165 have, seen from above, substantially the same dimensions of the same arrangement as the insulation walls 115 of the circuit 100.
    In this example, the upper face of the electrode 163, the upper faces of the studs 161, and the upper faces of the insulation rings 165 are substantially at the same level (that is to say substantially coplanar) and together form a continuous surface. substantially planar, forming the connection face of the circuit 150. Thus, the connection face of the circuit 150 comprises alternating metal regions (the pads 161 and the electrode 163) and dielectric regions (the regions 165), forming a pattern identical or similar to the pattern formed by the metallic and dielectric regions of the connection face of the circuit 100.
    B16845 - DD18591
    FIG. 1B illustrates a step subsequent to the production of the circuits 100 and 150 of FIG. 1B, during which the LED circuit 100 is attached to the control circuit 150, connection side facing the connection side of the circuit control 150. During this step, the connection face of the LED circuit 100 (namely its lower face in the orientation of FIG. 1B) is fixed to the connection face of the control circuit 150 (namely its upper face in the orientation of FIG. 1B) so that each electrode 111 of the LED circuit 100 is in mechanical and electrical contact with a metal stud 161 of the control circuit 150, and so that the common electrode 113 of the LED circuit 100 is in mechanical and electrical contact with the electrode 163 of the control circuit 150.
    In this example, the connection face of the LED circuit 100 is fixed to the connection face of the control circuit 150 by direct hybrid bonding, that is to say by direct metal-metal bonding of the electrodes 111 of the circuit 100 on the pads of connection 161 of circuit 150 and of electrode 113 of circuit 100 on electrode 163 of circuit 150, and by direct dielectric-dielectric bonding of the insulation walls 115 of circuit 100 on the insulating rings 165 of circuit 150. By direct bonding, here is understood to be a molecular bonding, without the addition of adhesive material or solder at the interface between the LED circuit 100 and the control circuit 150.
    FIG. 1B further illustrates a step subsequent to the bonding of the LED circuit 100 to the control circuit 150, during which the support substrate 101 of the LED circuit 100 is removed. If a buffer layer was provided between the support substrate 101 and the semiconductor layer 105 of the LED circuit 100, the buffer layer can also be removed during this step, so as to expose the face of the semiconductor layer 105 opposite the circuit of control 150 (namely its upper face in the orientation of FIG. 1B). In this example, the display device is indeed intended to emit light from the side
    B16845 - DD18591 of its face opposite to the control circuit 150, namely its upper face in the orientation of FIG. IB.
    The provision of direct hybrid bonding between the LED circuit 100 and the control circuit 150 is advantageous in that it makes it possible to obtain a particularly precise alignment of the LED circuit 100 with respect to the control circuit 150. Indeed , in the case of direct bonding, once the two circuits are aligned, a simple contacting of the circuits is sufficient to freeze the final position of the LED circuit 100 relative to the control circuit 150. In other words, the bonding is instantaneous . This constitutes a difference compared to bonding with the addition of material, for example by soldering, in which a compression and / or heating step must be carried out after the alignment and bringing the two circuits into contact, which may lead to circuit misalignment.
    A problem which arises in the method described in relation to FIGS. 1A and 1B is that the occupancy rate of the connection face of the LED circuit 100 with metal (and consequently the occupancy rate of the face of connection of the control circuit 150 by metal, the connection faces of the two circuits being symmetrical) is relatively high, typically greater than 70%, and for example greater than 80%. Indeed, the connection face of the LED circuit 100 consists essentially of the metal of the electrodes 111 and 113 of the LEDs, the dielectric material of the insulation walls 115 occupying only a small portion of the connection face.
    In addition, the distribution of the metal on the connection face of the LED circuit 100 (and consequently the distribution of the metal on the connection face of the control circuit 150) is not homogeneous. Indeed, as it appears in FIGS. 1A and 1B, the metal grid forming the common electrode 113 of the LED circuit 100 can comprise a relatively wide peripheral frame, for example of width (distance between the outer edge and the inner edge of the frame) greater than the inter-pixel pitch (i.e. the center-to-center distance between two LEDs 103
    B16845 - DD18591 neighbors) of the device, for example of width greater than twice the inter-pixel pitch of the device. As a result, the occupation rate of the connection face of the LED circuit 100 by metal is higher at the periphery of the LED assembly than inside the LED array.
    To obtain a good quality direct hybrid bonding, it would be preferable for the occupancy rate of the connection faces of circuits 100 and 150 to be lower, and that the distribution of the metal on the connection faces of circuits 100 and 150 be more homogeneous. Indeed, prior to the actual bonding step, the connection faces of the circuits 100 and 150 are planarized by chemical mechanical polishing (CMP). The surface flatness obtained during this step conditions the quality of the direct hybrid bonding of the two circuits. However, to obtain good surface flatness, it is preferable that the occupation rate of the connection face by metal is relatively low, and that the distribution of the metal on the connection face is as homogeneous as possible.
    FIGS. 2A and 2B are sectional views schematically and partially illustrating successive steps of an example of a method for manufacturing an emissive LED display device according to one embodiment.
    FIG. 2A illustrates an initial step during which a first integrated circuit 200 comprising a plurality of LEDs is manufactured, separately, and a second integrated circuit 250, corresponding to the LED control circuit.
    The LED circuit 200 of Figure 2A includes the same elements as the LED circuit 100 of Figure IA, arranged in substantially the same manner. These elements will not be detailed again below.
    The LED circuit 200 in Figure 2A differs from the LED circuit 100 in Figure IA mainly in that it further comprises, on the side of its upper face, a connection structure 201, extending over substantially the entire surface of the circuit.
    B16845 - DD18591
    The connection structure 201 comprises a dielectric layer 203 covering the upper face of the common electrode 113, individual electrodes 111, and insulation walls 115 of the circuit (corresponding to the upper face or connection face of the circuit 100 of the Figure IA). By way of example, the lower face of the dielectric layer 203 is in contact with the upper face of the common electrode 113, with the upper face of the individual electrodes 111, and with the upper face of the insulating walls 115.
    The connection structure 201 further comprises a plurality of disjointed elementary metal connection pads 205, identical or similar, disposed in through cavities formed in the dielectric layer 203. The connection pads 205 extend vertically from the underside to the upper face of the dielectric layer 203. In this example, the upper face of the dielectric layer 201 and the upper faces of the metal pads 205 are substantially at the same level (that is to say substantially coplanar) and define a substantially continuous surface flat, forming the connection face of the circuit 200. In this example, the only metallic elements visible on the upper face of the connection structure 201 are the pads 205. The connection pads 205 are regularly distributed over the entire surface of the circuit 200. In top view, the connection pads 205 are for example arranged in a matrix in rows e t columns. By way of example, in top view, the same elementary pattern consisting of a pad 205 surrounded by a portion of the dielectric layer 203 is repeated periodically over the entire upper surface of the circuit, in the direction of the rows and LED matrix columns. By way of example, the inter-pad pitch pl (that is to say the center-to-center distance between two pads 205 adjacent to the connection structure 201) is substantially identical in the direction of the rows and columns of the matrix, and is substantially identical over the entire surface of the matrix. Preferably, seen from above, the occupancy rate of the structure of
    B16845 - DD18591 connection 201 by the metal studs is between 5 and 50%, for example of the order of 25%.
    In each LED 103 of the LED circuit 200 of FIG. 2A, the electrode 111 of the LED is in contact, by its upper face, with the lower face of at least one contact pad 205 of the connection structure 201. In addition, the common electrode 113 of the LED circuit is in contact, at the periphery of the LED assembly 103, with several pads 205 of the connection structure 201. In this example, the same pad 205 of the connection structure is only in contact with an electrode 111 or 113 of the LED circuit.
    In the example shown, the inter-plot pitch pl of the connection structure 201 is less than the inter-pixel pitch p2 of the circuit 200, so that, inside the set of LEDs 103, the common electrode 113 of the circuit is in contact with studs 205 of the connection structure 201. The embodiments described are however not limited to this particular case. As a variant, the inter-pad pitch pl of the connection structure 201 may be equal to or substantially equal to the inter-pixel pitch p2 of the circuit 200, in which case the common electrode 113 of the circuit is not in contact with pads 205 only at the periphery of the LED assembly 103, and not inside the LED assembly 103. Each connection pad 205 has for example, in top view, a surface smaller than the surface of the electrode 111 of a circuit LED. By way of example, the inter-pixel pitch p2 of the device is between 2 and 30 μm, and the width of the elementary LEDs is between 0.5 and 25 μm.
    The control circuit 250 of Figure 2B is similar to the control circuit 150 of Figure IB, except that, in the example of Figure 2B, the connection face of the control circuit is adapted to have the same pattern metallic and dielectric than the connection face of the LED 200 circuit.
    By way of example, the control circuit 250 of FIG. 2B comprises the same elements as the control circuit 150 of FIG. 1B, arranged in substantially the same way, and
    B16845 - DD18591 further comprises, on the side of its upper face, a connection structure 251 similar to the connection structure 201 of the LED circuit 200, extending over substantially the entire surface of the control circuit 250.
    In particular, the connection structure 251 comprises a dielectric layer 253 coating the upper face of the common electrode 163, individual electrodes 161, and insulation rings 165 of the circuit (corresponding to the upper face or connection face of the circuit 150 of Figure IA). By way of example, the lower face of the dielectric layer 253 is in contact with the upper face of the common electrode 163, with the upper face of the individual electrodes 161, and with the upper face of the insulation rings 165.
    The connection structure 251 further comprises a plurality of disjointed elementary metal connection pads 255, identical or similar, arranged in through cavities formed in the dielectric layer 253. The connection pads 255 extend vertically from the underside to the upper face of the dielectric layer 253. In this example, the upper face of the dielectric layer 251 and the upper faces of the metal pads 255 are substantially at the same level (that is to say substantially coplanar) and define a substantially continuous surface plane, forming the connection face of the circuit 250. In this example, the only metallic elements visible on the upper face of the connection structure 251 are the studs 255.
    In top view, the dimensions and the distribution of the connection pads 255 of the connection structure 251 of the control circuit 250 are identical or similar to the dimensions and the distribution of the connection pads 205 of the connection structure 201 of the control circuit LED 200.
    Thus, each pad 161 of the control circuit 250 of FIG. 2A is in contact, by its upper face, with the lower face of at least one contact pad 255 of the connection structure 251. In addition, the peripheral part of electrode
    B16845 - DD18591 common 163 of the control circuit 250 is in contact with several studs 255 of the connection structure 251.
    FIG. 2B illustrates a step subsequent to the production of the circuits 200 and 250 of FIG. 2A, during which the LED circuit 200 is attached to the control circuit 250, connection side facing the connection side of the circuit control 250. During this step, the connection face of the LED circuit 200 (namely its lower face in the orientation of FIG. 2B) is fixed to the connection face of the control circuit 250 (namely its upper face in the orientation of FIG. 2B) so that each connection pad 205 of the LED circuit 200 is in mechanical and electrical contact with a connection pad 255 of the control circuit 250.
    In this example, the connection face of the LED circuit 200 is fixed to the connection face of the control circuit 250 by direct hybrid bonding, that is to say by direct metal-metal bonding of the connection pads 205 of the circuit 200 on the connection pads 255 of the circuit 250, and by direct dielectric dielectric bonding of the dielectric layer 203 of the circuit 200 on the dielectric layer 253 of the circuit 250.
    FIG. 2B further illustrates a step subsequent to the bonding of the LED circuit 200 to the control circuit 250, during which the support substrate 101 of the LED circuit 100, and, if necessary, a buffer layer (not shown ) provided between the substrate 101 and the semiconductor layer 105, are removed so as to expose the face of the semiconductor layer 105 opposite the control circuit 250.
    An advantage of the embodiment of FIGS. 2A and 2B resides in the provision, on the LED circuit side 200, of a connection structure 201, and, on the control circuit side 250, of a corresponding connection structure 251, making it possible to obtain , at the connection faces of the two circuits, a distribution of the metallic patterns better suited to producing a good quality direct hybrid bonding than the distribution
    B16845 - DD18591 imposed, in the example of Figures IA and IB, by the constraints of current distribution and / or heat in the LED circuit. In particular, the connection structure 201 allows the occupancy rate of the connection face of the LED circuit 200 (and therefore the occupancy rate of the connection face of the control circuit 250 by metal) to be lower. the metal occupancy rate at the upper face of the metal electrodes 111 and 113 of the LED circuit. In addition, the connection structure 201 allows the distribution of the metal on the connection face of the LED circuit 200 (and consequently the distribution of the metal on the connection face of the control circuit 250) to be more homogeneous than the distribution of the metal at the upper face of the metal electrodes 111 and 113 of the LED circuit.
    Figures 3A, 3B, 3C, 3D, 3E, 3F and 3G are sectional views illustrating in more detail successive steps of an example of a method of manufacturing an emissive LED display device according to a mode of achievement. FIGS. 3A, 3B, 3C, 3D, 3E, 3F and 3G more particularly illustrate successive steps of an example of a method for manufacturing the LED circuit 200 described in relation to FIG. 2A.
    FIG. 3A illustrates a step during which is deposited successively, on the upper face of the support substrate 101, the semiconductor layer 105, the emissive layer 107 and the semiconductor layer 109 forming an active stack of LEDs. At this stage, the layers 105, 107 and 109 extend continuously over substantially the entire upper surface of the support substrate 101. The layers 105, 107 and 109 are for example deposited by epitaxy on the upper face of the support substrate 101. In practice, depending on the nature of the substrate 101, a stack of one or more buffer layers (not shown) can interface between the support substrate 101 and the lower semiconductor layer 105.
    FIG. 3A further illustrates a deposition step, on and in contact with the upper face of the semiconductor layer
    B16845 - DD18591
    109, a metal layer 111 forming an upper electrode of the active LED stack. In this example, the metal layer 111 is deposited continuously over substantially the entire upper surface of the layer 109. The metal layer 111 is for example deposited by physical vapor deposition (BVD). For example, the metal layer 111 is made of copper or titanium.
    FIG. 3B illustrates a step of forming trenches 301 extending vertically in the stack of layers obtained at the end of the steps of FIG. 3A, from the upper face of the stack, that is to say from the upper face of the metal layer 111. The trenches 301 pass entirely through the layers 111, 109 and 107 and are interrupted at an intermediate level of the lower semiconductor layer 105. When viewed from above, the trenches 301 form a continuous grid delimiting the different LEDs 103 of the circuit.
    FIG. 3C illustrates a step of depositing a dielectric layer 115, for example made of silicon oxide, over the entire upper surface of the structure obtained at the end of the steps of FIGS. 3A and 3B, that is to say on the sides and on the bottom of the trenches 301 and on the upper face of the upper electrodes 111 of the LEDs 103. The layer 115 is preferably deposited by a conformal deposition method, for example by deposition in successive monoatomic layers (ALD). By way of example, the thickness of the insulating layer 115 is between 10 nm and 1 μm.
    FIG. 3D illustrates a step of removing the dielectric layer 115 at the bottom of the trenches 301 and on the upper face of the electrodes 111 of the LEDs 103. During this step, the layer 115 is kept on the side walls of the trenches 301. For this , the layer 115 is for example etched by vertical anisotropic etching.
    Figure 3D further illustrates a step of removing, by etching, portions of the lower semiconductor layer 105
    B16845 - DD18591 located at the bottom of the trenches 301, so as to extend the trenches 301 to the upper face of the substrate 101, or if necessary, to the upper face of the buffer layer which interfaces between the substrate 101 and the semiconductor layer 105. At the end of this step, the various LEDs 103 are entirely electrically isolated from each other by the trenches 301.
    FIG. 3E illustrates a step of depositing a metallization 113, for example of copper or titanium, on the side walls and on the bottom of the trenches 301 obtained at the end of the steps of FIG. 3D. In the example shown, the metallization 113 completely fills the trenches 301. By way of example, the metallization 113 is produced by a damascene type method, comprising a step of depositing a metallic layer over the entire upper surface of the assembly, over a thickness sufficient to fill the trenches 301, followed by a step of mechanochemical polishing of the upper face of the assembly to planarize the upper face of the device and remove the portions of the metal layer surmounting the LEDs 103, up to to expose the upper face of the insulation walls 115 (so as to isolate the common electrode 113 from the electrodes 111).
    FIG. 3F illustrates a step of depositing the dielectric layer 203 of the connection structure 201, on and in contact with the upper face of the structure obtained at the end of the steps of FIG. 3E. The dielectric layer 203 is for example made of silicon oxide or of silicon nitride. The layer 203 is for example deposited by chemical vapor deposition (BVD), or by any other suitable deposition method. The dielectric layer 203 is initially deposited continuously over substantially the entire upper surface of the structure obtained at the end of the steps of FIG. 3E, that is to say on the upper face of the electrodes 113 and 111 and on the upper face of the 115 insulation walls of the circuit.
    FIG. 3F also illustrates a localized etching step of the dielectric layer 203, to form in the
    B16845 - DD18591 layer 203 of the through openings 303 opening onto the upper faces of the electrodes 111 and 113 and intended to contain the connection pads 205 of the connection structure 201.
    FIG. 3G illustrates a step of filling the openings 303 with metal, for example titanium or copper, to form the connection pads 205 of the connection structure 201. By way of example, the connection pads 205 are produced by a damascene type process, comprising a step of depositing a metal layer over the entire upper surface of the structure obtained at the end of the steps of FIG. 3F, over a thickness sufficient to fill the openings 303, followed by a mechanical chemical polishing step of the upper face of the structure in order to planarize the upper face of the circuit and remove the portions of the metal layer surmounting the dielectric layer 203 between the openings 303, so as to isolate the connection pads 205 from each other other. At the end of this step, an LED circuit 200 identical or similar to that of FIG. 2A is obtained, the upper face or connection face of which is substantially planar and comprises alternating metal regions (the pads 205) and of dielectric regions (the portions of the layer 203 laterally surrounding the pads 205).
    FIGS. 4A, 4B, 4C, 4D, 4E and 4F are sectional views illustrating successive steps of another example of a method of manufacturing an emissive LED display device according to one embodiment. FIGS. 4A, 4B, 4C, 4D, 4E and 4F more particularly illustrate successive steps of an example of a method of manufacturing an alternative embodiment of the LED circuit 200 described in relation to FIG. 2A.
    FIG. 4A illustrates a step identical or similar to the step described in relation to FIG. 3A, during which is deposited successively, on the upper face of the support substrate 101, the semiconductor layer 105, the emissive layer 107 and the semiconductor layer 109, forming an active stack of LEDs, then the metal electrode layer
    B16845 - DD18591
    111 on and in contact with the upper face of the semiconductor layer 109.
    FIG. 4B illustrates a step of forming trenches 401 extending vertically in the stack of layers obtained at the end of the steps of FIG. 4A, from the upper face of the stack, that is to say from the upper face of the metal layer 111. In this example, the trenches 401 pass entirely through the layers 111, 109, 107 and 105 and are interrupted on the upper face of the support substrate 101, or, where appropriate, on the face upper layer of a buffer layer interfacing between the substrate 101 and the semiconductor layer 105. When viewed from above, the trenches 401 form a continuous grid delimiting the various LEDs 103 of the circuit. It will be noted that in this example, the steps for forming a peripheral insulation wall 115 at the top of the LEDs 103, described in relation to FIGS. 3B, 3C and 3D, are not provided. Thus, at the end of the step of forming trenches in FIG. 4B, the sides of the layers 111, 109, 107 and 105 of the LEDs are exposed over their entire height.
    FIG. 4C illustrates a step of partially filling the trenches 401 with a metal layer 403. More particularly, in this example, the metal layer 403 fills the bottom of the trenches, up to a level below the upper face of the semiconductor layer 105 In other words, in each LED 103, the metal layer 403 is in contact with a lower part of the sides of the semiconductor layer 105 of the LED, over the entire periphery of the LED. The metal layer 403 is however not in contact with the upper part of the sides of layer 105, nor with the sides of layers 107, 109 and 111 of LEDs 103.
    FIG. 4D illustrates a step during which one finishes filling the trenches 401 with an insulating material 405, for example silicon oxide. By way of example, a layer of insulating material 405 is deposited over the entire upper surface of the structure obtained at the end of the steps of the
    B16845 - DD18591 FIG. 4C, that is to say on and in contact with the upper face of the metal layer 403, on and in contact with the upper part of the sides of layer 105 and the sides of layers 107, 109 and 111 of the LEDs 103, and on and in contact with the upper face of the electrodes 111 of the LEDs 103. As an example, the layer of material 405 is deposited on a thickness greater than the depth of the upper part of the trenches 401 not filled by the metal layer 403, so as to completely fill the trenches 401, then a mechanochemical polishing step is implemented to planarize the upper face of the structure and expose the upper face of the electrodes 111 of the LEDs 103.
    FIG. 4E illustrates a step of resuming an electrical contact on the metal layer 403. For this, firstly, in the insulating layer 405, from its upper face, a through opening opens out onto the upper face of the metal layer 413, for example at the periphery of the set of LEDs 103 of the circuit. The opening is then filled with a metal 407, for example by a damascene type process, so as to bring the contact back to the level of the upper face of the circuit. In the example shown, the contact recovery metallization 407 is arranged on the periphery of the LED assembly 103 and completely surrounds the LED assembly 103, but does not extend inside the LED assembly 103. Alternatively, the contact recovery metallization 407 may have a grid-like pattern, similar to that of the metal layer 403, extending not only around the periphery of the LED assembly 103 but also across the inside the set of LEDs 103, between neighboring LEDs of the circuit. At the end of this step, the metallizations 403 and 407 define the common electrode 113 of the LED circuit.
    FIG. 4F illustrates a step of depositing the dielectric layer 203 of the connection structure 201, on and in contact with the upper face of the structure obtained at the end of the steps of FIG. 4E, then of forming the connection pads 205 in the dielectric layer 203,
    B16845 - DD18591 similarly to what has been described in relation to FIGS. 3F and 3G (formation of through openings opening onto the upper faces of metallizations 111 and 407, and filling of the openings with metal to form the studs 205).
    At the end of this step, an LED circuit is obtained
    200 'similar to the circuit 200 of FIG. 2A, except that, in the circuit 200', an insulator 405 thicker than the peripheral insulation walls 115 of the circuit 200 separates the LEDs 103 from one another.
    Particular embodiments have been described.
    Various variants and modifications will appear to those skilled in the art. In particular, the embodiments described are not limited to the particular example described above in which the LEDs of the device are based on gallium nitride. More generally, the embodiments described can be applied to any other LED technology.
    权利要求:
    Claims (12)
    [1" id="c-fr-0001]
    1. Display device comprising a first integrated circuit (200; 200 ') comprising:
    a set of several light-emitting diodes (103), each diode comprising a vertical stack of a first semiconductor layer (105) of a first conductivity type and of a second semiconductor layer (109) of the second conductivity type, and the diodes being separated from each other by trenches (301; 401);
    for each diode, a first electrode (111) disposed on and in contact with the face of the second layer (109) opposite the first layer (105);
    a second electrode (113) common to said plurality of diodes, the second electrode extending in the trenches (301; 401) and at the periphery of the plurality of diodes and being in contact, in each diode, with the first semiconductor layer (105); and on the side of a face of the first circuit opposite the first semiconductor layer (105), a connection structure (201) comprising a dielectric layer (203) in which are arranged a plurality of identical or similar connection pads (205) , regularly distributed over the entire surface of the first circuit, each diode (103) having its first electrode (111) in contact with at least one stud (205) of the connection structure (201), and the second electrode (113) being in contact with several pads (205) of the connection structure (201) at the periphery of the plurality of diodes.
    [2" id="c-fr-0002]
    2. Device according to claim 1, further comprising a second integrated circuit (250) formed in and on a semiconductor substrate (151), the second circuit comprising, for each diode of the first circuit (200), a metal pad (161) intended to be connected to the first electrode (111) of the diode, and a metal electrode (163) intended to be connected to the second electrode (113) of the first circuit (200; 200 ').
    B16845 - DD18591
    [3" id="c-fr-0003]
    3. Device according to claim 2, wherein the first (200; 200 ') and second (250) circuits are fixed to each other by direct hybrid bonding so that each first electrode (111) of the first circuit ( 200; 200 ') is electrically connected to a metal pad (161) of the second circuit (250), and that the second electrode (113) of the first circuit (200; 200') is electrically connected to the electrode (163) of the second circuit (250).
    [4" id="c-fr-0004]
    4. Device according to claim 2 or 3, in which the second circuit (250) comprises a connection structure (251) comprising a dielectric layer (253) in which are arranged a plurality of identical or similar connection pads (255), regularly distributed over the entire surface of the second circuit, each metal pad (161) of the second circuit being in contact with at least one connection pad (255) of the connection structure (251) of the second circuit (250), and the electrode (163) of the second circuit being in contact with several connection pads (255) of the connection structure (251) of the second circuit (250) in a peripheral region of the electrode (163) of the second circuit.
    [5" id="c-fr-0005]
    5. Device according to any one of claims 2 to 4, in which the second circuit (250) comprises, for each metal pad (161) of the second circuit, an elementary control cell comprising one or more transistors, making it possible to control the current flowing in the corresponding diode (103) of the first circuit and / or a voltage applied across the corresponding diode (103) of the first circuit.
    [6" id="c-fr-0006]
    6. Device according to any one of claims 2 to 5, wherein the second circuit (250) is made in CMOS technology.
    [7" id="c-fr-0007]
    7. Device according to any one of claims 1 to 6, wherein the diodes (103) of the first circuit (200; 200 ') are diodes with gallium nitride.
    [8" id="c-fr-0008]
    8. Device according to any one of claims 1 to 7, in which, in the first circuit (200; 200 '), each
    B16845 - DD18591 light emitting diode (103) further includes an emissive layer (107) between the first (105) and second (109) semiconductor layers of the diode.
    [9" id="c-fr-0009]
    9. A method of manufacturing a display device according to any one of claims 1 to 8, in which the formation of the first circuit (200; 200 ') comprises the following successive steps:
    a) successively depositing, on one face of a support substrate (101), a vertical stack comprising, in order from said face of the substrate, the first (105) and second (109) semiconductor layers and a layer metallic (111);
    b) forming, from the face of the stack opposite the support substrate (101), trenches (301; 401) crossing said stack over its entire height and delimiting the different diodes (103) of the first circuit; and
    c) forming, in said trenches (301; 401), a metallization in contact, at each diode (103), with the first semiconductor layer (105) of the stack.
    [10" id="c-fr-0010]
    10. The method of claim 9, wherein step b) comprises a first step of partial formation of the trenches (301) to an intermediate level of the first semiconductor layer (105), followed by a step of depositing 'an insulating layer (115) on the sides of the trenches (301), followed by a step of extending the trenches to the underside of the first semiconductor layer (105).
    [11" id="c-fr-0011]
    11. The method of claim 10, wherein the metallization formed in step c) extends over the entire height of the trench (301).
    [12" id="c-fr-0012]
    12. The method as claimed in claim 9, in which the metallization formed in step c) extends over only part of the height of the trenches (401), up to an intermediate level of the first semiconductor layer (105), the upper part of the trenches (401) being filled with an insulating material (405).
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    同族专利:
    公开号 | 公开日
    CN112166505A|2021-01-01|
    EP3769339B1|2022-02-23|
    FR3079350B1|2020-03-27|
    WO2019180362A1|2019-09-26|
    US20210020688A1|2021-01-21|
    EP3769339A1|2021-01-27|
    KR20200133775A|2020-11-30|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    WO2016060676A1|2014-10-17|2016-04-21|Intel Corporation|Microled display & assembly|
    EP3024030A1|2014-11-18|2016-05-25|Commissariat A L'energie Atomique Et Aux Energies Alternatives|Optoelectronic device with light emitting diodes and method of manufacturing the same|
    WO2017068029A1|2015-10-22|2017-04-27|Commissariat A L'energie Atomique Et Aux Energies Alternatives|Microelectronic diode with optimised active surface|
    FR3102303A1|2019-10-22|2021-04-23|Commissariat A L'energie Atomique Et Aux Energies Alternatives|LED emissive display device|
    CN111863797A|2020-07-29|2020-10-30|京东方科技集团股份有限公司|Display substrate, manufacturing method thereof and display device|
    法律状态:
    2019-03-29| PLFP| Fee payment|Year of fee payment: 2 |
    2019-09-27| PLSC| Publication of the preliminary search report|Effective date: 20190927 |
    2020-03-31| PLFP| Fee payment|Year of fee payment: 3 |
    2021-03-30| PLFP| Fee payment|Year of fee payment: 4 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1852465|2018-03-22|
    FR1852465A|FR3079350B1|2018-03-22|2018-03-22|EMISSIBLE LED DISPLAY DEVICE AND METHOD FOR MANUFACTURING SUCH A DEVICE|FR1852465A| FR3079350B1|2018-03-22|2018-03-22|EMISSIBLE LED DISPLAY DEVICE AND METHOD FOR MANUFACTURING SUCH A DEVICE|
    CN201980034527.7A| CN112166505A|2018-03-22|2019-03-18|LED emission display device and method of manufacturing the same|
    US17/040,033| US20210020688A1|2018-03-22|2019-03-18|Led emissive display device and method for producing such a device|
    EP19717543.3A| EP3769339B1|2018-03-22|2019-03-18|Led emissive display device and method for producing such a device|
    PCT/FR2019/050608| WO2019180362A1|2018-03-22|2019-03-18|Led emissive display device and method for producing such a device|
    KR1020207030008A| KR20200133775A|2018-03-22|2019-03-18|LED light-emitting display device and method of producing such device|
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